feat: v3 Cortex-M0 port — status sync and migration plan #4

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opened 2026-04-06 23:27:44 -07:00 by pyr0ball · 0 comments

pyr0ball commented

2026-04-06 23:27:44 -07:00

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Background

A v3 prototype running on a Cortex-M0 @ 24MHz exists (developed by Loredan/Vsevolod Merenkov). The current codebase targets AVR ATmega328P/PB at 8MHz (internal oscillator). The M0 port has not been merged or formally tracked.

A related migration intent was filed as pyr0ball/pyr0piezo#21 (2019, ATSAMD21E Cortex-M0+) but never progressed beyond the issue. The v3 hardware prototype is newer and separate from that.

Why it matters

24MHz vs 8MHz triples the clock budget for the same ISR workload
M0 interrupt entry is ~16 cycles (~667ns @ 24MHz) with hardware register stacking — no AVR pipeline stall
Hardware DAC available on ATSAMD21 variants eliminates the PWM + RC filter pseudo-DAC used for VFOL and VCOMP references — cleaner, more stable voltage references with less ripple
Onboard USB enables firmware updates and serial config without a separate programmer
These improvements directly benefit the autotune pipeline (#3) — tighter timing margins and DAC precision make the sweep algorithm more reliable

Current unknowns

What MCU exactly? (ATSAMD21E was the 2019 target; confirm v3 hardware)
Does the v3 prototype run the existing firmware with minimal changes, or is it a partial rewrite?
Which features are working on the prototype vs. still stubbed?
Is there a hardware schematic/KiCad source for v3?
Is the firmware on a branch, fork, or local only?

Proposed next steps

Sync with Loredan to get current state of the prototype
Open a v3-m0 branch and commit whatever firmware exists, even if partial
Audit AVR-specific code paths that need porting:
- readVcc() / readVin() — AVR bandgap trick; M0 has a real ADC with selectable reference
- OCR2B / OC1A PWM references — replace with DAC output if available
- INT0 interrupt — remap to equivalent EXTI/EIC on SAMD
- EEPROM.h — replace with SAMD NVM/flash emulation
Parameterize timing constants by F_CPU so AVR and M0 can share the same autotune logic (#3)
Evaluate whether to keep AVR as a supported target long-term or deprecate in favor of M0 only

#2 — PID / autotune firmware mode
#3 — Autotune pipeline algorithm
pyr0ball/pyr0piezo#21 — original ARM migration intent (archived GitHub)

## Background A v3 prototype running on a Cortex-M0 @ 24MHz exists (developed by Loredan/Vsevolod Merenkov). The current codebase targets AVR ATmega328P/PB at 8MHz (internal oscillator). The M0 port has not been merged or formally tracked. A related migration intent was filed as pyr0ball/pyr0piezo#21 (2019, ATSAMD21E Cortex-M0+) but never progressed beyond the issue. The v3 hardware prototype is newer and separate from that. ## Why it matters - 24MHz vs 8MHz triples the clock budget for the same ISR workload - M0 interrupt entry is ~16 cycles (~667ns @ 24MHz) with hardware register stacking — no AVR pipeline stall - Hardware DAC available on ATSAMD21 variants eliminates the PWM + RC filter pseudo-DAC used for VFOL and VCOMP references — cleaner, more stable voltage references with less ripple - Onboard USB enables firmware updates and serial config without a separate programmer - These improvements directly benefit the autotune pipeline (#3) — tighter timing margins and DAC precision make the sweep algorithm more reliable ## Current unknowns - [ ] What MCU exactly? (ATSAMD21E was the 2019 target; confirm v3 hardware) - [ ] Does the v3 prototype run the existing firmware with minimal changes, or is it a partial rewrite? - [ ] Which features are working on the prototype vs. still stubbed? - [ ] Is there a hardware schematic/KiCad source for v3? - [ ] Is the firmware on a branch, fork, or local only? ## Proposed next steps 1. Sync with Loredan to get current state of the prototype 2. Open a `v3-m0` branch and commit whatever firmware exists, even if partial 3. Audit AVR-specific code paths that need porting: - `readVcc()` / `readVin()` — AVR bandgap trick; M0 has a real ADC with selectable reference - `OCR2B` / `OC1A` PWM references — replace with DAC output if available - `INT0` interrupt — remap to equivalent EXTI/EIC on SAMD - `EEPROM.h` — replace with SAMD NVM/flash emulation 4. Parameterize timing constants by `F_CPU` so AVR and M0 can share the same autotune logic (#3) 5. Evaluate whether to keep AVR as a supported target long-term or deprecate in favor of M0 only ## Related - #2 — PID / autotune firmware mode - #3 — Autotune pipeline algorithm - pyr0ball/pyr0piezo#21 — original ARM migration intent (archived GitHub)

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Reference: Circuit-Forge/easypiezi#4

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