PCB layout — merlin-bci-rev0 (ADS1299 EEG front-end) #24

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opened 2026-04-26 22:10:23 -07:00 by pyr0ball · 0 comments

pyr0ball commented

2026-04-26 22:10:23 -07:00

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Overview

Lay out the rev0 PCB for the Merlin BCI EEG front-end based on the finalized BOM.

Tool: Autodesk Fusion 360 Electronics workspace (Eagle-compatible; .lbr libraries work directly)
BOM file: hardware/bom/merlin-bci-rev0.csv
Target size: ≤100×100mm (JLCPCB Economic PCBA 4-layer)
Gerber output: hardware/gerbers/merlin-bci-rev0/
CPL/BOM output for JLCPCB PCBA: hardware/jlcpcb/

Fusion Electronics libraries needed

Alan has the ESP32-WROOM-32E library and BAV99 is in Fusion's built-in library. Still needed:

Part	Package	Source
ADS1299IPAGR	TQFP-64 (0.5mm pitch)	TI product page → CAD/CAE symbols → Eagle/Fusion (use TI's own — 0.5mm pitch land pattern must be exact)
REF3325AIDBZR	SOT-23-5	TI product page
TPS60403DBVR	SOT-23-5	TI product page
TLV1117-33DCYR	SOT-223	TI product page
R2D-0505/R	SIP-7 (2.54mm, 7-pin)	Recom datasheet — custom footprint needed (simple 2.54mm SIP)
USB4085-GF-A	USB-C mid-mount SMD	GCT SnapEDA → Eagle/Fusion format
2.048MHz crystal	3225 4-pad	Generic SMD crystal footprint from Fusion built-in lib

Note: Prefer TI's official CAD downloads over SnapEDA/Ultra Librarian for ICs — land patterns are authoritative.

MCP-assisted layout (optional)

The Fusion MCP server (official Autodesk, local) can be tunneled from the Windows laptop to the Linux dev machine:

ssh -N -L 8080:localhost:8080 alan@<laptop-ip>

Add to Claude Code MCP config → Claude can drive schematic capture and layout directly.

Layout notes

4-layer stackup: Top signal / GND / PWR / Bottom signal
Star ground: Single-point AGND–DGND bond via FB2 ferrite bead. Keep analog and digital grounds separate up to that point.
ADS1299 AVDD/AVSS decoupling: 10µF + 100nF × 3 per rail, placed as close as possible to U1 pins
Crystal: Keep Y1 + C_CLK1/2 within 5mm of ADS1299 CLK pin, away from SPI traces
Input traces: R_IN → C_AC → C_EMI → D_clamp → ADS1299: short, symmetric differential pairs
SPI traces: R_SPI series termination resistors at MCU end of trace, not ADS1299 end
Isolation barrier: R2D-0505/R output side (AVDD/AVSS/AGND) must be physically separated from DVDD/DGND plane; no copper pours crossing the isolation boundary
ESP32 module footprint: Castellated pads — Alan hand-solders on arrival; footprint must be correct but no paste layer needed on those pads
J2 electrode connectors: Panel-mount or Touchproof snap — route signal from J2 pads through series R_IN directly, minimize trace length before protection network

Deliverables

Fusion Electronics .fsch and .fbrd files committed to hardware/fusion/
DRC clean (no errors)
Gerbers exported to hardware/gerbers/merlin-bci-rev0/
JLCPCB-format BOM + CPL exported (omit ESP32, R2D-0505/R, connectors — hand-solder)
Board dimensions confirmed ≤100×100mm
3D render screenshot in PR description

References

TI ADS1299EEG-FE evaluation board schematic (layout reference for ADS1299 section)
Recom R2D-0505/R datasheet (SIP-7 pinout for isolation barrier)
hardware/bom/merlin-bci-rev0.csv (component list with full notes)

## Overview Lay out the rev0 PCB for the Merlin BCI EEG front-end based on the finalized BOM. **Tool:** Autodesk Fusion 360 Electronics workspace (Eagle-compatible; `.lbr` libraries work directly) **BOM file:** `hardware/bom/merlin-bci-rev0.csv` **Target size:** ≤100×100mm (JLCPCB Economic PCBA 4-layer) **Gerber output:** `hardware/gerbers/merlin-bci-rev0/` **CPL/BOM output for JLCPCB PCBA:** `hardware/jlcpcb/` --- ## Fusion Electronics libraries needed Alan has the ESP32-WROOM-32E library and BAV99 is in Fusion's built-in library. Still needed: | Part | Package | Source | |------|---------|--------| | ADS1299IPAGR | TQFP-64 (0.5mm pitch) | TI product page → CAD/CAE symbols → Eagle/Fusion (use TI's own — 0.5mm pitch land pattern must be exact) | | REF3325AIDBZR | SOT-23-5 | TI product page | | TPS60403DBVR | SOT-23-5 | TI product page | | TLV1117-33DCYR | SOT-223 | TI product page | | R2D-0505/R | SIP-7 (2.54mm, 7-pin) | Recom datasheet — custom footprint needed (simple 2.54mm SIP) | | USB4085-GF-A | USB-C mid-mount SMD | GCT SnapEDA → Eagle/Fusion format | | 2.048MHz crystal | 3225 4-pad | Generic SMD crystal footprint from Fusion built-in lib | **Note:** Prefer TI's official CAD downloads over SnapEDA/Ultra Librarian for ICs — land patterns are authoritative. --- ## MCP-assisted layout (optional) The Fusion MCP server (official Autodesk, local) can be tunneled from the Windows laptop to the Linux dev machine: ``` ssh -N -L 8080:localhost:8080 alan@<laptop-ip> ``` Add to Claude Code MCP config → Claude can drive schematic capture and layout directly. --- ## Layout notes - **4-layer stackup:** Top signal / GND / PWR / Bottom signal - **Star ground:** Single-point AGND–DGND bond via FB2 ferrite bead. Keep analog and digital grounds separate up to that point. - **ADS1299 AVDD/AVSS decoupling:** 10µF + 100nF × 3 per rail, placed as close as possible to U1 pins - **Crystal:** Keep Y1 + C_CLK1/2 within 5mm of ADS1299 CLK pin, away from SPI traces - **Input traces:** R_IN → C_AC → C_EMI → D_clamp → ADS1299: short, symmetric differential pairs - **SPI traces:** R_SPI series termination resistors at MCU end of trace, not ADS1299 end - **Isolation barrier:** R2D-0505/R output side (AVDD/AVSS/AGND) must be physically separated from DVDD/DGND plane; no copper pours crossing the isolation boundary - **ESP32 module footprint:** Castellated pads — Alan hand-solders on arrival; footprint must be correct but no paste layer needed on those pads - **J2 electrode connectors:** Panel-mount or Touchproof snap — route signal from J2 pads through series R_IN directly, minimize trace length before protection network ## Deliverables - [ ] Fusion Electronics `.fsch` and `.fbrd` files committed to `hardware/fusion/` - [ ] DRC clean (no errors) - [ ] Gerbers exported to `hardware/gerbers/merlin-bci-rev0/` - [ ] JLCPCB-format BOM + CPL exported (omit ESP32, R2D-0505/R, connectors — hand-solder) - [ ] Board dimensions confirmed ≤100×100mm - [ ] 3D render screenshot in PR description ## References - TI ADS1299EEG-FE evaluation board schematic (layout reference for ADS1299 section) - Recom R2D-0505/R datasheet (SIP-7 pinout for isolation barrier) - `hardware/bom/merlin-bci-rev0.csv` (component list with full notes)

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Reference: Circuit-Forge/raven#24

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